Generally, an interconnect structure incorporated into the IC includes one or more levels of metal lines to connect the electronic devices of the IC to one another and to external connections. An interlayer dielectric is placed between the metal levels of the IC for insulation.
Typically, an additive patterning technique, known as a Damascene process, is used to fabricate a copper interconnect. In this process, the underlying silicon oxide insulating layer is patterned to form trenches. The trenches in the insulating layer are filled with a thick layer of copper, and chemical-mechanical polishing (CMP) is used to remove the copper that extends above the top of the insulating layer. Copper within the trenches of the insulating layer is not removed and becomes the patterned conductor.
Typically, in a Dual Damascene (DD) process, two features of copper interconnect are formed at once, e.g., a trench overlying a via, may both be filled with a single copper deposition. Typically, the DD interconnects need a liner for adhesion and a hermetic barrier to protect the metal. The liner in the DD interconnects is typically non-conducting and adds to the line resistance.
As the size of the IC decreases, the spacing between the metal lines decreases. This leads to increase in the coupling capacitance between the metal lines. Increase in the coupling capacitance between the metal lines has a negative impact on signal transmission along metal lines. Furthermore, increase in the coupling capacitance increases energy consumption of the integrated circuit.
Another patterning technique to form an interconnect is a subtractive patterning technique. However, subtractive interconnects are not self-aligned to the via below. Generally, subtractive patterning of the metal lines is done independently of the vias below, so that location of the via below the metal layer cannot be accurately determined. In conventional subtractive patterning techniques, the vias below are mis-aligned to the lines above that increases via resistance and leads to potential shorting to the wrong metal line. The via-line misalignment causes device failures, decreases yield and increases manufacturing cost.